Research Interests

Computer Architecture - On Chip Networks ( NoC ) - VLSI Physical Design

Education

  • July 2012 - Present : Pursuing PhD in Computer Science at Indian Institute of Technology Madras(IIT M).
  • July 2006- July 2008 : M.Tech in VLSI at International Institute of Information Technology Hyderabad(IIIT H).
    my IIIT-H home page
  • July 2002- July 2006 : B.Tech E.C.E at Srinivasa Institute of Technology and Management Studies(SITAMS).

    • Resume

    will be updated soon

    Publications

    2016 – Gnaneswara Rao Jonna, Vamana Murthi Thuniki, and Madhu Mutyam. "CASCADE: Congestion Aware Switchable Cycle Adaptive Deflection Router". 29th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2016), Nuremberg, Germany, 2016

    2014 – Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, and Madhu Mutyam. "MinBSD : Minimally Buffered Single-Cycle Deflection Router for Mesh NoCs". IEEE/ACM International Conference on Design, Automation & Test in Europe (DATE), Dresden, Germany, pp. 1-4, 2014

    Positions Held

  • July 2014 : TA for CSD and Lead TA for CS1100 at IIT M.
  • Jan 2014 : TA for PCA and Lead TA for CS1100 at IIT M.
  • July 2013 : TA for CSD and Lead TA for CS1100 at IIT M.
  • Jan 2013 : Lead TA for CS1100 at IIT M.
  • July 2012 : TA for CS1100 at IIT M.
  • Assistant Professor at CREC.
  • Assistant Professor at KEC.
  • Sep 2008 - May 2010 : CAE at Synopsys EDA Hyderabad.
  • Student Intern at Synopsys EDA Hyderabad.
  • TA for Formal Foundations in VLSI at IIIT H.
  • Project Associate at NARL, DOS, GOI.
    • This template downloaded form