Hello, welcome to my home page. I am an associate professor in the Department of Computer Science and Engineering at Indian Institute of Technology, Madras. My current research focus is on multicore architectures, specifically, issues related to memory system design and networks-on-chip. I am associated with Programming Languages, Architecture, and Compilers Education (PACE) Lab. I am a senior member of IEEE and ACM. My Erdos number is 3 (Gheorghe Paun -> Solomon Marcus -> Paul Erdos).

Dr. Madhu Mutyam
BSB 356
Dept. of CSE
IIT Madras
Chennai - 600 036
Ph: +91 44 2257 4379
Fax: +91 44 2257 4352
Email: madhu AT cse
DOT iitm DOT ac DOT in
6/2014-5/2015: I am on sabbatical leave from IIT Madras to work at Intel Bangalore.
    • CS6560: Parallel Computer Architecture (S'14, F'12, F'11, F'10)
    • CS1100: Computational Engineering (S'14, S'12, S'10)
    • CS4100: Computer System Design (F'13, F'12)
    • CS4110: Computer System Design Lab (F'13, F'12, F'11)
    • CS6200: Advanced Computer Architecture (S'13)
    • CS6600: Computer Architecture (S'12, S'11)
    • CS2610: Assembly Language Programming Lab (S'11)
    • CS2600: Computer Organization (S'11)
    • CS2300: Switching Theory and Digital Design (F'10, F'09, F'08)
    • CS2310: Digital Logic and Design Lab (F'10, F'09, F'08)
    • CS6230: CAD for VLSI (S'10, S'09, S'08)
    Current Research Students:
    • Ph.D.
      • T.V. Kalyan (7/2009) -- Main memory optimizations
      • K. Raghavendra (1/2010) -- Main memory optimizations
      • Tripti S. Warrier (1/2010) -- Managing large shared caches in multicore systems
      • Gnaneswar Rao Jonna (7/2012) -- Network-on-chip
      • S.R. Swami Saranam Chongala (7/2014)
    • M.S. (Research)
      • R. Prasanna Venkatesh Rengasamy(7/2011) -- Multithreading with NoCs: Tackling heavy congestion (Thesis submitted)
      • Pritam Majumder (1/2012)
      • Sudharsan (1/2013)
      • A. Nizamudheen (1/2014)
      • Patil Rakesh Ravindra (1/2014) (Co-guide: Dr. Shankar Balachandran)
    Graduated Research Students:
    • Ph.D.
      • John Jose (2014) -- Congestion Management Techniques for Adaptive Routers in Mesh Network on Chips
    • M.S. (Research)
      • Aditya Arvind Kajwe (2014) -- Improving fairness in memory scheduling using a team of learning automata
      • Arpit Joshi (2011) -- Low cost routers for network-on-chip architectures
      • Nayan Mujadiya (2011) -- Instruction scheduling for VLIW processors under variation scenario
      • T.V. Kalyan (2009) -- Low power design techniques
      • Abu Saad Papa (2008) -- Power management of chip multiprocessors
      • Md. Abid Hussain (2008) -- Process variation tolerant caches
    Research Funding:
    • (01/2014--12/2016) Department of Science and Technology, Govt. of India: Exploring Techniques to Optimize Main Memory of Multi-Core Systems.
    Selected Recent Publications: (click here for the complete list)
    • Tripti S. Warrier, K. Raghavendra, and Madhu Mutyam. SkipCache: Application Aware Cache Management for Chip Multi-Processors. IET Computers & Digital Techniques (CDT), 2015 (Accepted).
    • T.V. Kalyan, K. Ravi, and Madhu Mutyam. EFGR: An Enhanced Fine Grain Granularity Refresh Feature for High Performance DDR4 DRAM Devices. ACM Transactions on Architecture and Code Optimization (TACO), 11(3):31, 2014. (Invited to make a presentation in the 10th HiPEAC Conference, Amsterdam 2015)
    • Pritam Majumder, T.V. Kalyan, and Madhu Mutyam. SFFMap: Set-First Fill Mapping for an Energy Efficienct Pipelined Data Cache. 32nd IEEE International Conference on Computer Design (ICCD), pp. 104-109, 2014.
    • John Jose and Madhu Mutyam. Implementation and Analysis of History Based Output Channel Selection Function for Adaptive Routers in Mesh NoCs. ACM Transactions on Design Automation of Electronic Systems (TODAES), 19(4):35 (2014).
    • Prasanna Venkatesh and Madhu Mutyam. Using Packet Information for Efficient Communication in NoCs. International Symposium on Networks-on-Chip (NOCS), pp. 143-150, 2014.
    • Sudharsan, T.V. Kalyan, and Madhu Mutyam. Data Remapping for an Energy Efficienct Burst Chop in DRAM Memory Systems.. ACM Student Research Competition, International Conference on Parallel Architectures and Compilation Techniques (ACM-SRC), August 24-27, 2014 (Bronze medal winner).
    • Aditya Kajwe and Madhu Mutyam. Improving Fairness in Memory Scheduling Using a Team of Learning Automata. The Memory Forum, Co-located with ISCA, June 14, 2014, Minneapolis, Minnesota.
    • Raghavendra, Tripti Warrier, and Madhu Mutyam. SAMO: Store Aware Memory Optimizations. ACM International Conference on Computing Frontiers (CF), Article No. 33, 2014.
    • Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, and Madhu Mutyam. Minimally Buffered Single-Cycle Deflection Router for Mesh NoCs. IEEE/ACM International Conference on Design, Automation & Test in Europe (DATE), pp. 1-4, 2014.
    • T.V. Kalyan, K. Ravi, and Madhu Mutyam. Scattered Refresh: An Alternative Refresh Mechanism to Reduce Refresh Cycle Time. 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 598-603, 2014.
    Technical Program Committee Member:
    • 2015: ISVLSI; IPDPS (Architecture track); PARCOMPTECH; VLSI Design;
    • 2014: ICCD; CASES; ICPP; Memory Architecture and Organization Workshop (Program Committee Co-Chair); ISVLSI (Special Session -- Track Co-Chiar); IndoSys; VLSI Design (Track Co-Chair)
    • 2013: ICPP; VLSI Design (Track Co-Chair); ISVLSI
    • 2012: VLSI Design; ISVLSI
    • 2011: VLSI Design (Track Co-Chair); ISVLSI (Finance Chair); VLSI-SoC
    • 2010: VLSI Design; ISVLSI; VLSI-SoC
    • 2009: VLSI Design; ISVLSI

    Think. Don't just do. Set aside time to explore ideas.
    Thinking is more important than reading.

    Last modified: 11th Mar, 2015 Free counter and web stats