Current Research Students:
- CS6560: Parallel Computer Architecture (S'14, F'12, F'11, F'10)
- CS1100: Computational Engineering (S'14, S'12, S'10)
- CS4100: Computer System Design (F'13, F'12)
- CS4110: Computer System Design Lab (F'13, F'12, F'11)
- CS6200: Advanced Computer Architecture (S'13)
- CS6600: Computer Architecture (S'12, S'11)
- CS2610: Assembly Language Programming Lab (S'11)
- CS2600: Computer Organization (S'11)
- CS2300: Switching Theory and Digital Design (F'10, F'09, F'08)
- CS2310: Digital Logic and Design Lab (F'10, F'09, F'08)
- CS6230: CAD for VLSI (S'10, S'09, S'08)
Graduated Research Students:
- John Jose (1/2009) -- Congestion issues in network-on-chips
- T.V. Kalyan (7/2009) -- Main memory optimizations
- K. Raghavendra (1/2010) -- Main memory optimizations
- Tripti S. Warrier (1/2010) -- Managing large shared caches in multicore systems
- Gnaneswar Rao Jonna (7/2012) -- Network-on-chip
- M.S. (Research)
- Aditya Arvind Kajwe (7/2010)
- R. Prasanna Venkatesh (7/2011)
- Pritam Majumder (1/2012)
- Sudharsan (1/2013)
QIP Short Term Course:
- M.S. (Research)
- Arpit Joshi (2011) -- Low cost routers for network-on-chip architectures
- Nayan Mujadiya (2011) -- Instruction scheduling for VLIW processors under variation scenario
- T.V. Kalyan (2009) -- Low power design techniques
- Abu Saad Papa (2008) -- Power management of chip multiprocessors
- Md. Abid Hussain (2008) -- Process variation tolerant caches
- Recent Trends in Computer Architecture, Dec 17-21, 2012, IIT Madras.
Selected Recent Publications: (click here for the complete list)
- (01/2012--12/2013) UKIERI Research Award: Power Efficient and High Performance Data Prefetching Techniques for Multi-core Processors.
- (09/2010--08/2013) Defence Research and Development Organization, Govt. of India: Low Cost Routers for Netwoks-on-Chip Architectures.
Technical Program Committee Member:
- Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, and Madhu Mutyam. Minimally Bufferred Single-Cycle Deflection Router for Mesh NoCs. IEEE/ACM International Conference on Design, Automation & Test in Europe (DATE), Mar 24-28, 2014, Dresden, Germany (accepted as a poster).
- T.V. Kalyan, K. Ravi, and Madhu Mutyam. Scattered Refresh: An Alternative Refresh Mechanism to Reduce Refresh Cycle Time. 19th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 20-23, 2014, Singapore (accepted).
- Arpit Joshi, Prasanna Venkatesh, and Madhu Mutyam. Prevention Slot Flow-Control Mechanism for Low Latency Torus Network-on-Chip. IET Computers & Digital Techniques (CDT), October 2013 (13 pages).
- Bhawna Nayak, John Jose, and Madhu Mutyam. SLIDER: Smart Late Injection DEflection Router for Mesh NoCs. 31st IEEE International Conference on Computer Design (ICCD), pp. 377-383, 2013.
- John Jose, Bhawna Nayak, D. Kranthi Kumar, and Madhu Mutyam. DeBAR: Deflection based adaptive router with minimal buffering. IEEE/ACM International Conference on Design, Automation & Test in Europe (DATE), pp. 1583-1588, 2013.
- John Jose, K.V. Mahathi, J. Shiva Shankar, and Madhu Mutyam. TRACKER: A low overhead adaptive NoC router with load balancing selection strategy. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 564-568, 2012.
- Madhu Mutyam. Fibonacci codes for crosstalk avoidance. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 20(10):1899-1903, 2012.
- VLSI Design: 2014 - Track Co-Chair; 2013 - Track Co-Chair; 2012; 2011 - Track Co-Chair; 2009.
- ICPP: 2014; 2013.
- ISVLSI: 2013; 2012; 2011 - Treasurer; 2010; 2009.
- VLSI-SoC: 2011; 2010.
Think. Don't just do. Set aside time to explore ideas.
Thinking is more important than reading.