Hello, welcome to my home page. I am an associate professor in the Department of Computer Science and Engineering at Indian Institute of Technology, Madras. My current research focus is on multicore architectures, specifically, issues related to memory system design and networks-on-chip. I am associated with Programming Languages, Architecture, and Compilers Education (PACE) Lab. I am a senior member of IEEE and ACM. My Erdos number is 3 (Gheorghe Paun -> Solomon Marcus -> Paul Erdos).

Dr. Madhu Mutyam
BSB 356
Dept. of CSE
IIT Madras
Chennai - 600 036
Ph: +91 44 2257 4379
Fax: +91 44 2257 4352
Email: madhu AT cse
DOT iitm DOT ac DOT in
6/2014-5/2015: I am on sabbatical leave from IIT Madras to work at Intel Bangalore.
    Teaching:
    • CS6560: Parallel Computer Architecture (S'14, F'12, F'11, F'10)
    • CS1100: Computational Engineering (S'14, S'12, S'10)
    • CS4100: Computer System Design (F'13, F'12)
    • CS4110: Computer System Design Lab (F'13, F'12, F'11)
    • CS6200: Advanced Computer Architecture (S'13)
    • CS6600: Computer Architecture (S'12, S'11)
    • CS2610: Assembly Language Programming Lab (S'11)
    • CS2600: Computer Organization (S'11)
    • CS2300: Switching Theory and Digital Design (F'10, F'09, F'08)
    • CS2310: Digital Logic and Design Lab (F'10, F'09, F'08)
    • CS6230: CAD for VLSI (S'10, S'09, S'08)
    Current Research Students:
    • Ph.D.
      • John Jose (1/2009) -- Congestion management techniques for adaptive routers in mesh network on chips (Thesis submitted)
      • T.V. Kalyan (7/2009) -- Main memory optimizations
      • K. Raghavendra (1/2010) -- Main memory optimizations
      • Tripti S. Warrier (1/2010) -- Managing large shared caches in multicore systems
      • Gnaneswar Rao Jonna (7/2012) -- Network-on-chip
      • S.R. Swami Saranam Chongala (7/2014)
    • M.S. (Research)
      • Aditya Arvind Kajwe (7/2010) -- Improving fairness in memory scheduling using a team of learning automata (Thesis submitted)
      • R. Prasanna Venkatesh Rengasamy(7/2011) -- Multithreading with NoCs: Tackling heavy congestion (Thesis submitted)
      • Pritam Majumder (1/2012)
      • Sudharsan (1/2013)
      • A. Nizamudheen (1/2014)
      • Patil Rakesh Ravindra (1/2014) (Co-guide: Dr. Shankar Balachandran)
    Graduated Research Students:
    • M.S. (Research)
      • Arpit Joshi (2011) -- Low cost routers for network-on-chip architectures
      • Nayan Mujadiya (2011) -- Instruction scheduling for VLIW processors under variation scenario
      • T.V. Kalyan (2009) -- Low power design techniques
      • Abu Saad Papa (2008) -- Power management of chip multiprocessors
      • Md. Abid Hussain (2008) -- Process variation tolerant caches
    Research Funding:
    • (01/2014--12/2016) Department of Science and Technology, Govt. of India: Exploring Techniques to Optimize Main Memory of Multi-Core Systems.
    • (01/2012--08/2014) UKIERI Research Award: Power Efficient and High Performance Data Prefetching Techniques for Multi-core Processors.
    Selected Recent Publications: (click here for the complete list)
    • T.V. Kalyan, K. Ravi, and Madhu Mutyam. EFGR: An Enhanced Fine Grain Granularity Refresh Feature for High Performance DDR4 DRAM Devices. ACM Transactions on Architecture and Code Optimization (TACO), 2014.
    • John Jose and Madhu Mutyam. Implementation and Analysis of History Based Output Channel Selection Function for Adaptive Routers in Mesh NoCs. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2014.
    • Prasanna Venkatesh and Madhu Mutyam. Using Packet Information for Efficient Communication in NoCs. International Symposium on Networks-on-Chip (NOCS), September 17-19, 2014, Ferrera, Italia.
    • Aditya Kajwe and Madhu Mutyam. Improving Fairness in Memory Scheduling Using a Team of Learning Automata. The Memory Forum, Co-located with ISCA, June 14, 2014, Minneapolis, Minnesota.
    • Raghavendra, Tripti Warrier, and Madhu Mutyam. SAMO: Store Aware Memory Optimizations. ACM International Conference on Computing Frontiers (CF), May 20-22, 2014, Cagliari, Italy.
    • Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, and Madhu Mutyam. Minimally Buffered Single-Cycle Deflection Router for Mesh NoCs. IEEE/ACM International Conference on Design, Automation & Test in Europe (DATE), pp. 1-4, 2014.
    • T.V. Kalyan, K. Ravi, and Madhu Mutyam. Scattered Refresh: An Alternative Refresh Mechanism to Reduce Refresh Cycle Time. 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 598-603, 2014.
    • Arpit Joshi, Prasanna Venkatesh, and Madhu Mutyam. Prevention Slot Flow-Control Mechanism for Low Latency Torus Network-on-Chip. IET Computers & Digital Techniques (CDT), 7(6):304-316, 2013.
    • Bhawna Nayak, John Jose, and Madhu Mutyam. SLIDER: Smart Late Injection DEflection Router for Mesh NoCs. 31st IEEE International Conference on Computer Design (ICCD), pp. 377-383, 2013.
    • John Jose, Bhawna Nayak, D. Kranthi Kumar, and Madhu Mutyam. DeBAR: Deflection based adaptive router with minimal buffering. IEEE/ACM International Conference on Design, Automation & Test in Europe (DATE), pp. 1583-1588, 2013.
    Technical Program Committee Member:
    Think. Don't just do. Set aside time to explore ideas.
    Thinking is more important than reading.

    Last modified: 15th Aug, 2014 Free counter and web stats