Teaching:
- CS6600: Computer Architecture (Spring 2012, Spring 2011)
- CS1100: Computational Engineering (Spring 2012)
- CS6560: Parallel Computer Architecture (Fall 2011, Fall 2010)
- CS4110: Computer System Design Lab (Fall 2011)
- CS2610: Assembly Language Programming Lab (Spring 2011)
- CS2600: Computer Organization (Spring 2011; Jointly with Prof. S. Das)
- CS2300: Switching Theory and Digital Design (Fall 2010, Fall 2009, Fall 2008)
- CS2310: Digital Logic and Design Lab (Fall 2010, Fall 2009, Fall 2008)
- CS6230: CAD for VLSI (Spring 2010, Spring 2009, Spring 2008)
Current Research Students:
- Ph.D.
- John Jose (1/2009) -- Congestion issues in network-on-chips
- T.V. Kalyan (7/2009) -- Architectural techniques to exploit emerging memory technologies
- K. Raghavendra (1/2010) -- Cache coherency issues in heterogeneous multicore systems
- Tripti S. Warrier (1/2010) -- Managing large shared caches in multicore systems
- M.S. (Research)
- Aditya Arvind Kajwe (7/2010)
- R. Prasanna Venkatesh (7/2011)
- Pritam Majumder (1/2012)
Graduated Research Students:
- M.S. (Research)
- Arpit Joshi (2011) -- Low cost routers for network-on-chip architectures
- Nayan Mujadiya (2011) -- Instruction scheduling for VLIW processors under variation scenario
- T.V. Kalyan (2009) -- Low power design techniques
- Abu Saad Papa (2008) -- Power management of chip multiprocessors
- Md. Abid Hussain (2008) -- Process variation tolerant caches
Research Funding:
- (01/2012--12/2013) UKIERI Research Award: Power efficient and high performance data prefetching techniques for multi-core processors.
- (09/2010--08/2012) Defence Research and Development Organization, Govt. of India: Low Cost Routers for Netwoks-on-Chip Architectures.
- (06/2009--05/2012) Department of Science and Technology, Govt. of India: Energy Efficient Cache Architectures.
Recent Publications: (click here for the
complete list)
- C.J. Janraj, T.V. Kalyan, Tripti Warrier, and Madhu Mutyam. Way sharing set associative cache architecture. 25th International Conference on VLSI Design, 7th-11th January, 2012, Hyderabad, India.
- Madhu Mutyam. Fibonacci codes for crosstalk avoidance. IEEE Transactions on Very Large Scale Integration Systems, 2012 (accepted).
- John Jose, J. Shiva Shankar, K.V. Mahathi, D.Kranthi Kumar, and Madhu Mutyam. BOFAR: Buffer occupancy factor based adaptive router for mesh NoCs. 4th ACM International Workshop on Network on Chip Architectures (NoCArc), pp. 23-28, 2011.
- Kartikey Mittal, Arpit Joshi, and Madhu Mutyam. Timing variation-aware scheduling and resource binding in high-level synthesis. ACM Transactions on Design Automation of Electronic Systems, 16(4), Articl No. 40, 19 pages, October, 2011.
- Arpit Joshi and Madhu Mutyam. Prevention flow-control for low latency torus networks-on-chip. ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 41-48, 2011.
Technical Program Committee Member:
ISVLSI (2012, 2011 - Treasurer, 2010, 2009), VLSI Design (2012, 2011 - Track Co-Chair, 2009), VLSI-SoC (2011, 2010)
Think. Don't just do. Set aside time to explore ideas.
Thinking is more important than reading.
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