Current Research Students:
- CS4100: Computer System Design (F'13, F'12)
- CS4110: Computer System Design Lab (F'13, F'12, F'11)
- CS6200: Advanced Computer Architecture (S'13)
- CS6560: Parallel Computer Architecture (F'12, F'11, F'10)
- CS6600: Computer Architecture (S'12, S'11)
- CS1100: Computational Engineering (S'12)
- CS2610: Assembly Language Programming Lab (S'11)
- CS2600: Computer Organization (S'11)
- CS2300: Switching Theory and Digital Design (F'10, F'09, F'08)
- CS2310: Digital Logic and Design Lab (F'10, F'09, F'08)
- CS6230: CAD for VLSI (S'10, S'09, S'08)
Graduated Research Students:
- John Jose (1/2009) -- Congestion issues in network-on-chips
- T.V. Kalyan (7/2009) -- Main memory optimizations
- K. Raghavendra (1/2010) -- Main memory optimizations
- Tripti S. Warrier (1/2010) -- Managing large shared caches in multicore systems
- Gnaneswar Rao Jonna (7/2012) -- Network-on-chip
- M.S. (Research)
- Aditya Arvind Kajwe (7/2010)
- R. Prasanna Venkatesh (7/2011)
- Pritam Majumder (1/2012)
- Sudharsan (1/2013)
QIP Short Term Course:
- M.S. (Research)
- Arpit Joshi (2011) -- Low cost routers for network-on-chip architectures
- Nayan Mujadiya (2011) -- Instruction scheduling for VLIW processors under variation scenario
- T.V. Kalyan (2009) -- Low power design techniques
- Abu Saad Papa (2008) -- Power management of chip multiprocessors
- Md. Abid Hussain (2008) -- Process variation tolerant caches
- Recent Trends in Computer Architecture, Dec 17-21, 2012, IIT Madras.
Recent Publications: (click here for the
- (01/2012--12/2013) UKIERI Research Award: Power Efficient and High Performance Data Prefetching Techniques for Multi-core Processors.
- (09/2010--08/2012) Defence Research and Development Organization, Govt. of India: Low Cost Routers for Netwoks-on-Chip Architectures.
Technical Program Committee Member:
- John Jose, Bhawna Nayak, D. Kranthi Kumar, and Madhu Mutyam. DeBAR: Deflection based adaptive router with minimal buffering. IEEE/ACM International Conference on Design, Automation & Test in Europe (DATE), pp. 1583-1588, 2013.
- Tripti S Warrier, Anupama B, and Madhu Mutyam. An application-aware cache replacement policy for last-level caches. 26th International Conference on Architecture of Computing Systems (ARCS), pp. 207-219, 2013.
- John Jose, K.V. Mahathi, J. Shiva Shankar, and Madhu Mutyam. TRACKER: A low overhead adaptive NoC router with load balancing selection strategy. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 564-568, 2012.
- K. Raghavendra, Tripti Warrier, and Madhu Mutyam. SkipCache: Miss-rate aware cache management. ACM International Conference on Parallel Architecture and Compilation Techniques (PACT), ACM SRC Abstracts, pp. 481, 2012.
- C.J. Janraj, T.V. Kalyan, Tripti Warrier, and Madhu Mutyam. Way sharing set associative cache architecture. 25th International Conference on VLSI Design (VLSID), pp. 251-256, 2012.
- Madhu Mutyam. Fibonacci codes for crosstalk avoidance. IEEE Transactions on Very Large Scale Integration Systems, 20(10):1899-1903, 2012.
ICPP (2013), ISVLSI (2013, 2012, 2011 - Treasurer, 2010, 2009), VLSI Design (2013 - Track Co-Chair, 2012, 2011 - Track Co-Chair, 2009), VLSI-SoC (2011, 2010)
Think. Don't just do. Set aside time to explore ideas.
Thinking is more important than reading.