Current Research Students:
- CS6630: Secure Processor Microarchitecture (S'20)
- CS6600: Computer Architecture (F'19, F'18, S'12, S'11)
- CS6620: Advanced Computer Organization and Architecture with Lab (F'19)
- CS2600: Computer Organization and Architecture (S'19)
- CS2610: Computer Organization and Architecture Lab (S'19)
- CS2300: Foundations of Computer Systems Design (F'18)
- CS2310: Foundations of Computer Systems Design Lab (F'18)
- CS6560: Parallel Computer Architecture (S'18, S'16, S'14, F'12, F'11, F'10)
- CS1100: Introduction to Programming (F'17, F'15, S'14, S'12, S'10)
- CS4100: Computer System Design (F'16, F'15, F'13, F'12)
- CS4110: Computer System Design Lab (F'16, F'15, F'13, F'12, F'11)
- NPTEL-MOOC: Computer Architecture (1st Jul - 31st Aug, 2015)
- CS6200: Advanced Computer Architecture (S'13)
- CS2610: Assembly Language Programming Lab (S'11)
- CS2600: Computer Organization (S'11)
- CS2300: Switching Theory and Digital Design (F'10, F'09, F'08)
- CS2310: Digital Logic and Design Lab (F'10, F'09, F'08)
- CS6230: CAD for VLSI (S'10, S'09, S'08)
Graduated Research Students:
- M. Praseetha
- Praveen Kumar Alapati
- S.R. Swami Saranam Chongala
- M.S. (Research)
- Abdun Nihaal
- Sai Deepak Bezawada
- Joe Augustine
Recent Publications: (click here for the complete list)
- K. Raghavendra (2017) (Assistant Professor, Dept. of CSE, IIT Tirupati)
- Tripti S. Warrier (2016) (Assistant Professor, Dept. of Electronics, Cochin University of Science and Technology, Kerala)
- T.V. Kalyan (2015) (Assistant Professor, Dept. of CSE, IIT Ropar)
- John Jose (2014) (Assistant Professor, Dept. of CSE, IIT Guwahati)
- M.S. (Research)
- Puneet Saraf (2020) (Silicon Design Engineer, AMD, Bengaluru)
- Sayantan Ray (2019) (Senior Software Engineer, Samsung R&D Institute India, Bengaluru)
- J. Sudharsan (2017) (Technical Staff Member, VMwareSoftware, Bengaluru)
- Pritam Majumder (2016) (PhD Student, Dept. of CSE, Texas A&M University)
- Prasanna Venkatesh Rengasamy (2016) (SoC Architect, Apple, California)
- Aditya Arvind Kajwe (2014) (Software Engineer, Paypal, Chennai)
- Arpit Joshi (2011) (Researcher, Intel, Portland)
- Nayan Mujadiya (2011) (R&D Engineer, Synopsys, Bengaluru)
- T.V. Kalyan (2009) (Assistant Professor, Dept. of CSE, IIT Ropar)
- Abu Saad Papa (2008) (Product Development Lead, Invention Labs, Chennai)
- Md. Abid Hussain (2008) (Design Engineer, Xilinx, Hyderabad)
Technical Program Committee Member:
- Praveen Alapati, T.V. Kalyan, Madhu Mutyam. A Scalable and Energy-Efficient Concurrent Binary Search Tree with Fatnodes. IEEE Transactions Sustainable Computing, 2020 (Accepted).
- Debiprasanna Sahoo, Shivani Tripathy, Manoranjan Satpathy, Madhu Mutyam. Post-Model Validation of Victim DRAM Caches. IEEE International Conference on Computer Design (ICCD), pp. 305-308, 2019.
- Praveen Alapati, Madhu Mutyam, Swamy Saranam. Concurrent Treaps and Impact of Locking Objects. New Generation Computing, 2019 (Accepted).
- Puneet Saraf, Madhu Mutyam. Endurance Enhancement of Write-Optimized STT-RAM Caches. International Symposium on Memory Systems (MEMSYS), Washington DC, USA, Sept 30-Oct 3, 2019.
- Sayantan Ray, Madhu Mutyam. VSCC: Variable Sized Cache Block Compaction. International Conference on Parallel Architectures and Compilation Techniques (PACT), Seattle, USA, Sept 21-25, 2019 (Poster).
- Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha Roop. Formal Modeling and Verification of a Victim DRAM Cache. ACM Transactions on Design Automation of Electronic Systems (TODAES), 24(2), Article No. 20, 2019.
- Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam. ReDRAM: A Reconfigurable DRAM Cache for GPGPUs. IEEE Computer Architecture Letters (CAL), 17(2): 213-216, 2018.
- Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, Ramesh S, and Partha Roop. Formal Modeling and Verification of Controllers for a Family of DRAM Caches. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 37 (11):2485-2496, 2018 [Also presented in CODES+ISSS, Sep 30 - Oct 5, 2018, Torino, Italy].
- Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, Laxmi Narayan Bhuyan. CAMO: A Novel Cache Management Organization of GPGPUs. 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 215-220, 2018.
- Raghavendra K, Biswabandan Panda, Madhu Mutyam. MBZip: Multi-Block Data Compression. ACM Transactions on Architecture and Code Optimization (TACO), 14(4), Article No. 42, 2017 (29 pages) [Also included in the paper track of HiPEAC-2018, Jan 22-24, 2018, Manchester, UK].
- 2019: ISVLSI; VLSI Design
- 2018: ICCD; ISVLSI; VLSI Design; ASP-DAC
- 2017: ICCD; ISVLSI; VDAT
- 2016: ICCD; ISVLSI; VDAT
- 2015: ICCD; iNIS; ISVLSI; IPDPS (Architecture track); PARCOMPTECH; VLSI Design;
- 2014: ICCD; CASES; ICPP; Memory Architecture and Organization Workshop (Program Committee Co-Chair); ISVLSI (Special Session -- Track Co-Chiar); IndoSys; VLSI Design (Track Co-Chair)
- 2013: ICPP; VLSI Design (Track Co-Chair); ISVLSI
- 2012: VLSI Design; ISVLSI
- 2011: VLSI Design (Track Co-Chair); ISVLSI (Finance Chair); VLSI-SoC
- 2010: VLSI Design; ISVLSI; VLSI-SoC
- 2009: VLSI Design; ISVLSI
Think. Don't just do. Set aside time to explore ideas.
Thinking is more important than reading.