CS2600 : Computer Organization and Architecture (3-1-0-0-6-10-10)

Objective:
  • To learn about the internal organization of CPU and physical memory unit, different types of instruction set architecture used in CPUs, hardware support for operating system functions, architectures of scalar pipelined processor, superscalar processor, multi-threaded processor and multi-core processor, and programming models for multi-threaded and multi-core processors.
Syllabus:
  • Introduction to Structured Computer Organization: Digital hardware level, Microarchitecture level, Operating system level, System programming level and Application programming level, Differences between computer organization and computer architecture.
  • Instruction Set Architecture: Arithmetic, logical and comparison instructions, Addressing modes, Data movement instructions, Control transfer instructions, Instruction representation, Instruction decoding, Control unit, Atomic instructions, Stack frames, Function calls and parameter passing, CISC and RISC architectures, Flynn's taxonomy, SIMD architecture.
  • Memory Hierarchy: Architectural register file, Dynamic RAM (DRAM) based main memory unit -- Synchronous DRAM, Double Data Rate Synchronous DRAM; Static RAM based cache memory unit -- Locality of reference, Cache organization, Cache hit and miss, Direct mapped cache, Set-associative mapped cache, Cache controller, Multi-level caches; Hierarchy of physical memory - Average access time; Secondary memory -- Organization of hard disk.
  • Support for Operating System: Virtual memory -- Paging, Page table, Translation look-aside buffer, Page fault handling; User and supervisor level execution environments, Multi-stack based execution environment, Exceptions - Traps and Interrupts, Interrupt service routines; Secure execution environment design -- Inter-process and intra-process protection with privilege levels, Protection in multi-layered operating system.
  • Processor Microarchitecture: Pipelined instruction processor -- Stage balancing, Structural hazards, Data hazards and Control hazards, Operand forwarding, Static branch prediction; Instruction level parallelism -- Superscalar processors, Dynamic scheduling of instructions, Out-of-order execution of instructions, Register renaming, Register spilling, Memory aliasing, Multi-port memory units, Zero-cycle load instructions; Branch prediction unit for dynamic branch prediction -- 2-bit predictor, Correlation-based predictor, Tournament predictor, Branch target buffer, Multi-threaded processor architecture.
  • Multi-Core Procerssors: Multi-core processor architecture, Cache coherency protocols -- Snooping based protocols, Concurrent programming models for multi-core processors -- Parallel random access machines.
Text Book:
  • W. Stallings. Computer Organization and Architecture, Pearson Education, 10th Edition, 2016.
Reference Books:
  • J.L. Hennessy and D.A. Patterson. Computer Organization and Design - The Hardware/Software Interface, Elsevier, 5th Edition, 2014.
  • J.L. Hennessy and D.A. Patterson. Computer Architecture - A Quantitative Approach, Elsevier, 6th Edition, 2017.
  • C. Hamacher, Z. Vranesic, S. Zaky and N. Manjikian. Computer Organization and Embedded Systems, McGraw-Hill, 6th Edition, 2012.
Evaluation Mechanism:
  • 5 Class Tests (15%)
  • 2 Quizzes (40%)
  • End Semester Exam (45%)
Lecture Schedule: C Slot (CS36)
Last modified: Jan 6th, 2019