CS6630: Secure Processor Microarchitecture (4-0-0-0-8-12-12)
Objective:
- To provide a detailed discussion on processor microarchitectural vulnerabilities and measures to mitigate them.
Course Contents:
- Processor Microarchitecture: Memory hierarchy, Out-of-order execution, Branch prediction, Speculative execution, Prefetching, Superscalar processors, Multithreaded Processors, Multi-core Processors.
- Timing Attacks: Side-channel attacks, Covert-channel attacks, Cache timing attack models -- Prime-and-Probe, Flush-and-Reload, Flush-and-Flush, Evict-and-Time, Cache Collision; Out-of-order execution timing attack -- Meltdown; Speculative execution attack -- Spectre; Hardware prefetch-aided timing channel attacks.
- Secure Memory Components: Timing attacks on memory components -- cache, main memory,
memory controllers, translation look-aside buffers (TLBs), Coherence directories; Secure cache
architectures, Secure cache coherence directories, Secure TLBs, Secure memory controller
designs, Mitigating memory bus side-channel attack, Exploiting hardware prefetching to mitigate
cache timing attacks.
- Defending Speculative Execution Attacks: Timing attacks in speculative execution
processors, Techniques to mitigate speculative execution attacks, Timing attacks on the branch
prediction units (BPUs), Secure BPUs.
Reference Books/Material:
- J. Szefer and M. Martonosi. Principles of Secure Processor Architecture Design. Morgan and Claypool Publishers, 2018.
- Papers from the top-rated conferences: ISCA, HPCA, MICRO, ASPLOS, CCS, USENIC Security.
Evaluation Mechanism:
- 5 Programming Assignments (15%) -- Once every two weeks.
- Paper Reading (15%) -- Once every two weeks.
- Mid Semester Exam (30%) -- 14th Mar 2020.
- Project (45%) -- Final evaluation during the last instruction week.
Lecture Schedule: B Slot (Mon: 9:00am-9:50am; Tue: 8:00am-8:50am; Wed: 12:00pm-12:50pm; Fri: 11:00am-11:50am)
Venue: CS24
Last modified: Dec 31st, 2019