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CS2310: Digital Logic And Design Laboratory | |
July - November, 2015 |
Manual
Lab Assignments List
| Lab Assignments | ||||
| SL No. | Assignments | Date | No of weeks | Details |
| 1 | Introduction to CS2310-Lab, NAND and it’s characteristics | 4/08/2015 | 1 | -- |
| 2 |
a) Design Ex-OR gate using NAND and NOR Gates. b) Design Majority gates using NAND and NOR gates. |
11/08/2015 | 1 |
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| 3 | a) Design a circuit that evaluates the determinant of a 2 X 2 binary matrix (Note : State any assumptions made about input and output representations). b) Design a circuit that takes two unsigned 2-bit numbers (a and b), and displays one of greater(a > b), lesser (a < b) or equal (a == b) signals. |
18/08/2015 | 1 |
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| 4 | Half Adder,Full Adder and Ripple Carry Adder Implementation. | 25/09/2015 | 1 |
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| 5 | Plane Parking problem implementation using Mux and Decoder. | 01/09/2015 | 1 |
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| 6 | Cycle Detection in Graphs | 08/09/2015 | 1 |
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| 7 | a) Add two 2 digit BCD numbers. Display using 7-segment displays. b) Subtract two 2-digit BCD numbers. |
22/09/2015 | 1 |
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| 8 |
Convert a 4-bit number from one mode to another. Handle the invalid cases for both a) Gray code to 6-3-1-1 code. b) Excess-3 code to 2-out-of-5 code. |
29/09/2015 |
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| 9 | Write and verify Verilog code for 8-bit Multiplier using carry save adders.
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6/10/2015 | 1 | -- |
| 10 | a) Design two SR latches, one using NOR gate and other using NAND gates. b) Convert the 2 latches into D latches. |
13/10/2015 | 1 |
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| 11 | a) Design Master Slave J-K Flip flop. b) A positive edge-triggered T flip flop using logic gates. |
20/10/2015 | 1 |
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| 12 | a) Design a 2-bit Synchronous up counter using D flip flop IC's. Display the output on a 7-segment LED display . b) Counter using asynchronous flip flop arbitary sequence. |
27/10/2015 | 1 | -- | 13 | Sequence generator using shift registers. |
27/10/2015 | 1 | -- | 14 | Write and Verify Verilog code for elevator design. |
27/10/2015 | 1 | -- |
| References |
| C. H. Roth, Fundamental s of Logic design, Jaico Publishers, 1998. |
| V. P. Nelson, H.T. Nagle, E.D. Caroll and J.D. Irwin, Digital Logic Circuit Analysis and Design, Prentice Hall International, 1995. |
| S. Brown and Z Vranesic, Fundamentals of Logic Design with VHDL Design, Tata McGraw-Hill , 2000. |
| F.J. Hill and G.R.Peterson, Computer Aided Logical Design with Emphasis on VLSI, John Wiley & Sons, 1993. |
| C. Hamacher, Z. Vranesic and S. Zaky, Computer Organization, McGraw-Hill, 2002. |
| J.P. Hayes, Computer Architecture and Organization, McGraw-Hill, 1998. |
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Syllabus: 
Lab Exam-1 Date: November 3, 2015
Lab Exam-2 Date: November 10, 2015