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Undergraduate Core

CS2300: Foundations of Computer Systems Design

This course helps students design and implement a simple but functional processor microarchitecture from first principles. It moves from digital logic and combinational design to sequential systems, stored-program execution, instruction-set design, and a complete working CPU implementation.

CS2300 course image
Latest Offering Diwali'23 (July - Nov, 2023)
Instructor Ayon Chakraborty
Materials Moodle
Focus Digital design to microarchitecture

Teaching Feedback

Diwali'22 · 0.85 Diwali'23 · 0.82 Online BS offering

The course is divided into two broad components: digital design and processor design. Students first learn logic-related fundamentals and core circuit-design skills, then connect stored-program execution to instruction-set architecture, machine code, and a hardware platform capable of storing and executing code.

The accompanying video playlist is based on the online IIT Madras BS Data Science systems-bucket offering. The classroom version is positioned to help students transition smoothly into CS2600 and later CS6600 by first learning how to build a correct computer before worrying about performance and then state-of-the-art architectural optimization.

The playlist follows the online IIT Madras BS Data Science version of the course and works as a companion to the in-class material hosted on Moodle.

Lecture Roadmap

Modules are arranged in course order. Expand a module to inspect its lecture-level breakup.

Lectures 1-7 Module 1 Introductory Topics Click to expand

Computing System

  • Lecture 1: Continuing from CS1111. Source code, compilation, disassembly, machine code, and the idea of designing a complete computer from first principles.
  • Lecture 2: What is a computer? From earlier generations to smartphones, with Moore's Law as context.
  • Lecture 3: Why digital? Information representation.

CMOS Transistors and Logic Gates

  • Lecture 4: Transistors as switches, two-state abstraction, switching logic, and CMOS using NMoS and PMoS.
  • Lecture 5: NOT, NAND, AND via NAND + NOT, and transistor networks.
  • Lecture 6: In-class CMOS implementation tutorial for Boolean functions such as XOR.
  • Lecture 7: Timing delays, fan-out, static and dynamic power, and the broader VLSI picture.
Lectures 8-17 Module 2 Combinational Logic Design Click to expand

Self-study prerequisite: Boolean algebra basics, axioms, distributive law, De Morgan's laws, and related notes.

  • Lecture 8: Boolean algebra simplification with numerical examples.
  • Lecture 9: Canonical logic expressions: SOP and POS.
  • Lecture 10: Worked examples from past GATE problems.
  • Lecture 11: What combinational circuits are needed for a computer? Motivation toward the ALU.
  • Lecture 12: Mux, demux, encoder, decoder, and priority encoder with software parallels.
  • Lecture 13: Binary addition, half and full adders, and negative number representation.
  • Lecture 14: Complement systems and extending adders to subtraction.
  • Lecture 15: K-maps, glitches, and simplification for glitch-free design.
  • Lecture 16: Seven-segment LED logic and design exercises.
  • Lecture 17: PLA-based design and homework problems.
Lectures 18-30 Module 3 Sequential Logic Design Click to expand

Sequential Logic Elements

  • Lecture 18: Circuits with feedback, R-S and gated D-latches, excitation tables.
  • Lecture 19: D-latches, D flip-flops, clocking, and excitation tables.
  • Lecture 20: JK latch behavior, racing, and master-slave design.

Design Principles for Sequential Logic

  • Lecture 21: Two-bit up/down counter design using master-slave JK flip-flops.
  • Lecture 22: T flip-flops and comparative discussion of D, T, and JK-based designs; ASM charts.
  • Lecture 23: More sequential designs including up/down counters.

Counters, Dividers, Registers, and FSMs

  • Lecture 24: BCD counters, Johnson and ring counters, and frequency dividers.
  • Lecture 25: Registers, shift registers, and their applications.
  • Lecture 26: Register-based memory organization, addressing, bus design, tri-state buffers, and register banks as ALU scratchpads.
  • Lecture 27: Introduction to FSMs via a traffic-light-controller case study.
  • Lecture 28: Moore versus Mealy FSM design and practice problems.
  • Lecture 29: FSM sequence detectors.
  • Lecture 30: Miscellaneous FSM problems such as coin-change and vending-machine controllers.
Lectures 31-42 Module 4 Computer System Design Click to expand

This segment includes concepts taught in the lab, microinstructions and control words, automated control-signal generation, the design of the control unit as both microprogrammed logic and a hardware FSM, a long implementation workshop, and an introduction to Verilog.

  • Lecture 31: History of CPU evolution from mainframes and minicomputers to PCs; IBM S/360, PDP series, Altair 8800, MOS 6502, Xerox Alto, x86, and related milestones.
  • Lecture 32: Architecting the simple processor Gajendra-1: datapath, register organization, ALU, and bus access using controlled tri-state buffers.
  • Lecture 33: From high-level software to machine code; ISA design and the Gajendra-1 assembly language.
  • Lecture 34: Stored-program execution: fetch path with PC and MAR.
  • Lecture 35: Stored-program execution: decode path, IR, MAR, MDR, and memory.
  • Lecture 36: Manual control-signal generation for moving data across memory, buses, and registers; multiplication via repeated addition.
  • Lecture 37: Software-based control logic, ring counters in the control circuit, and T-states for multicycle execution.
  • Lecture 38: Implementation details for Gajendra-1 and Logisim demonstration.
  • Lecture 39: More Logisim implementation details and control logic as a hardware FSM.
  • Lecture 40: Programming Gajendra-1 for multiplication, Fibonacci, and arithmetic-series display.
  • Lecture 41: Addressing modes, function calls, and the call stack.
  • Lecture 42: Course conclusion, summary, and homebrew CPU projects.

Final design exercise: Gajendra-1 CPU

Books