Current Research Students:
- CS2600: Computer Organization and Architecture (S'21, S'19)
- CS2610: Computer Organization and Architecture Lab (S'21, S'19)
- CS6600: Computer Architecture (F'20, F'19, F'18, S'12, S'11)
- CS6620: Advanced Computer Organization and Architecture with Lab (F'20, F'19)
- CS6630: Secure Processor Microarchitecture (S'20)
- CS2300: Foundations of Computer Systems Design (F'18)
- CS2310: Foundations of Computer Systems Design Lab (F'18)
- CS6560: Parallel Computer Architecture (S'18, S'16, S'14, F'12, F'11, F'10)
- CS1100: Introduction to Programming (F'17, F'15, S'14, S'12, S'10)
- CS4100: Computer System Design (F'16, F'15, F'13, F'12)
- CS4110: Computer System Design Lab (F'16, F'15, F'13, F'12, F'11)
- NPTEL-MOOC: Computer Architecture (1st Jul - 31st Aug, 2015)
- CS6200: Advanced Computer Architecture (S'13)
- CS2610: Assembly Language Programming Lab (S'11)
- CS2600: Computer Organization (S'11)
- CS2300: Switching Theory and Digital Design (F'10, F'09, F'08)
- CS2310: Digital Logic and Design Lab (F'10, F'09, F'08)
- CS6230: CAD for VLSI (S'10, S'09, S'08)
Graduated Research Students:
- M. Praseetha
- S.R. Swami Saranam Chongala
- M.S. (Research)
- Adhar Dua
- Abdun Nihaal
- Sai Deepak Bezawada
Recent Publications: (click here for the complete list)
- Praveen Kumar Alapati (2020) (Assistant Professor, Dept. of CSE, College of Engineering, Mahindra Ecole Centrale, Hyderabad)
- K. Raghavendra (2017) (Assistant Professor, Dept. of CSE, IIT Tirupati)
- Tripti S. Warrier (2016) (Assistant Professor, Dept. of Electronics, Cochin University of Science and Technology, Kerala)
- T.V. Kalyan (2015) (Assistant Professor, Dept. of CSE, IIT Ropar)
- John Jose (2014) (Assistant Professor, Dept. of CSE, IIT Guwahati)
- M.S. (Research)
- Joe Augustine (2021) (Silicon Design Engineer, AMD, Benaluru)
- Puneet Saraf (2020) (Silicon Design Engineer, AMD, Bengaluru)
- Sayantan Ray (2019) (Senior Software Engineer, Samsung R&D Institute India, Bengaluru)
- J. Sudharsan (2017) (Technical Staff Member, VMwareSoftware, Bengaluru)
- Pritam Majumder (2016) (PhD Student, Dept. of CSE, Texas A&M University)
- Prasanna Venkatesh Rengasamy (2016) (SoC Architect, Apple, California)
- Aditya Arvind Kajwe (2014) (Software Engineer, Paypal, Chennai)
- Arpit Joshi (2011) (Researcher, Intel, Portland)
- Nayan Mujadiya (2011) (R&D Engineer, Synopsys, Bengaluru)
- T.V. Kalyan (2009) (Assistant Professor, Dept. of CSE, IIT Ropar)
- Abu Saad Papa (2008) (Product Development Lead, Invention Labs, Chennai)
- Md. Abid Hussain (2008) (Design Engineer, Xilinx, Hyderabad)
Technical Program Committee Member:
- Joe Augustine, Raghavendra K, John Jose, Madhu Mutyam. Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors. IEEE International Conference on Computer Design (ICCD), pp. 239 - 246, 2020.
- S.R. Swamy Saranam Chongala, Sumitha George, Hariram Thirucherai Govind, Jagadish Kotra, Madhu Mutyam, John Samson, Mahmut Kandemir, Vijaykrishnan Narayanan. Optimization of Inter Cache Traffic Entanglement in Tagless Caches with Tiling Opportunities. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 39(11):3881-3892, 2020.
- Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam. Fuzzy Fairness Controller for NVMe SSDs. ACM International Conference on Supercomputing (ICS), Article No. 22, pp 1-12, 2020.
- Praveen Alapati, T.V. Kalyan, Madhu Mutyam. A Scalable and Energy-Efficient Concurrent Binary Search Tree with Fatnodes. IEEE Transactions Sustainable Computing, 5(4):468-484, 2020.
- Praveen Alapati, Madhu Mutyam, Swamy Saranam. Concurrent Treaps and Impact of Locking Objects. New Generation Computing, 38(1):187-212, 2020.
- Debiprasanna Sahoo, Shivani Tripathy, Manoranjan Satpathy, Madhu Mutyam. Post-Model Validation of Victim DRAM Caches. IEEE International Conference on Computer Design (ICCD), pp. 305-308, 2019.
- Puneet Saraf, Madhu Mutyam. Endurance Enhancement of Write-Optimized STT-RAM Caches. International Symposium on Memory Systems (MEMSYS), pp. 101-113, 2019.
- Sayantan Ray, Madhu Mutyam. POSTER: Variable Sized Cache Block Compaction. International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 471-472, 2019.
- Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha Roop. Formal Modeling and Verification of a Victim DRAM Cache. ACM Transactions on Design Automation of Electronic Systems (TODAES), 24(2):1-23, Article No. 20, 2019.
- 2020: HiPC (Architecture Track)
- 2019: ISVLSI; VLSI Design
- 2018: ICCD; ISVLSI; VLSI Design; ASP-DAC
- 2017: ICCD; ISVLSI; VDAT
- 2016: ICCD; ISVLSI; VDAT
- 2015: ICCD; iNIS; ISVLSI; IPDPS (Architecture track); PARCOMPTECH; VLSI Design;
- 2014: ICCD; CASES; ICPP; Memory Architecture and Organization Workshop (Program Committee Co-Chair); ISVLSI (Special Session -- Track Co-Chiar); IndoSys; VLSI Design (Track Co-Chair)
- 2013: ICPP; VLSI Design (Track Co-Chair); ISVLSI
- 2012: VLSI Design; ISVLSI
- 2011: VLSI Design (Track Co-Chair); ISVLSI (Finance Chair); VLSI-SoC
- 2010: VLSI Design; ISVLSI; VLSI-SoC
- 2009: VLSI Design; ISVLSI
Think. Don't just do. Set aside time to explore ideas.
Thinking is more important than reading.