John Jose

Ph.D Scholar, PACE Laboratory (BSB-331A), Department of Computer Science & Engineering

Hello, welcome to my homepage. I am a fifth year Ph.D scholar in Department of Computer Science and Engineering at Indian Institue of Technology, Madras. I am working with Dr. Madhu Mutyam, in the field of Computer Architecture. My research focus is on Network on Chip Architectures.

During office hours you can find me in PACE Lab(BSB-331A), CSE Dept-IIT Madras.

Office Contact: +91-44-22575392 (PACE Lab Extension)
email: johnjose004 [at] gmail [dot] com OR johnjose [at] cse [dot] iitm [dot] ac [dot] in
Residential Address: Quarters# : G3-6, Madras Avenue, IIT Madras Campus, Chennai-36.

Research Interests

Congestion aware NoC router designs in multi core processors.
Energy efficient bufferless NoC router design in multi core procesoors.


John Jose, Bhawna Nayak, Kranthikumar D., Madhu Mutyam, DeBAR : Deflection Based Adaptive Router with Minimal Buffering, to appear in proceedings of IEEE/ACM International Conference on Design, Automation and Test in Euope (DATE-13), Grenoble, France, March 18-22, 2013.
John Jose, Working With Adaptive NoC Routers, to appear in Ph.D Forum Abstracts of IEEE/ACM International Conference on Design, Automation and Test in Europe (Ph.D Forum @ DATE-2013), Grenoble, France, March 18-22, 2013.
John Jose, K.V. Mahathi, J.Shiva Shankar, Madhu Mutyam,TRACKER: A Low Overhead Adaptive NoC Router with Load Balancing Selection Strategy, in proceedings of the IEEE/ACM-International Conference on Computer Aided Design (ICCAD-12), SanJose, California, USA, November, 2012. pp:564-568. DOI
John Jose, J.Shiva Shankar, K.V. Mahathi, D. Kranthikumar, Madhu Mutyam, BOFAR: Buffer Occupancy Factor based Adaptive Router for Mesh NoCs, in proceedings of the 4th ACM International Workshop on Network on Chip Architectures (NoCArc-11) held in conjunction with the Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-44), Porto Alegre, Brazil, December, 2011, pp-23-28. DOI
John Jose, Madhu Mutyam, Implementation and Analysis of History Based Output Channel Selection Function for Adaptive Routers in Mesh NoCs, ACM Transactions on Design Automation of Electronic Systems (ACM-TODAES)- Special Issue on Networks on Chip: Architecture, Tools, and Methodologies, Sept 2013 edition. (communicated - awaiting review)

Professional Experience

Faculty in department of computer science & engineering, Viswajyothi College of Engineering and Technology , Kerala from June 2003 till Dec 2008.
Teaching Assistant in Department of Computer Science and Engineering, IIT Madras since January 2009.

Educational Profile

Ph.D (CSE) - Indian Institue of Technology, Madras, Tamil Nadu. (pursuing since 2009 January)
M.Tech (CSE) - (Vellore Institute of Technology, (VIT University), Tamil Nadu. (2004-2006)
B.Tech (CSE) - College of Engineerig Adoor, (Cochin University), Kerala. (1999-2003)

Professional Society Memberships

Student member IEEE, Student member ACM, Life member ISTE, Life member CSI, Member ACM-SIGDA

Courses Completed

Last modified on 6th March 2013.