PACE Lab : Programming Languages, Architecture, Compilers Education LaboratoryLink to Lab Webpage

Research AreasMemory System Design, Network-on-chip architectures, Cache Design in Multicore, Program Analysis, Parallelization, Code Optimization.
MembersFaculty : Madhu Mutyam, V. Krishna Nandivada, Rupesh Nasre, Vijay Natarajan, K. C. Sivaramakrishnan.

Students/Scholars :
Project Staffs :

Recent Publications
  • Optimizing remote data transfers in X10.  
           Arun Thangamani , V. Krishna Nandivada
          Appeared in Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, PACT 2018, Limassol, Cyprus, November 01-04, 2018, pp.27:1-27:15, Nov 2018
  • NumLock: Towards Optimal Multi-Granularity Locking in Hierarchies.  
           Saurabh Kalikar , Rupesh Nasre
          Appeared in Proceedings of the 47th International Conference on Parallel Processing, ICPP 2018, Eugene, OR, USA, August 13-16, 2018, pp.75:1-75:10, Aug 2018
  • Multi-granularity Locking in Hierarchies with Synergistic Hierarchical and Fine-Grained Locks.  
           K. Ganesh , Saurabh Kalikar , Rupesh Nasre
          Appeared in Euro-Par 2018: Parallel Processing - 24th International Conference on Parallel and Distributed Computing, Turin, Italy, August 27-31, 2018, Proceedings, Lecture Notes in Computer Science, Vol 11014, pp.546-559, Aug 2018
  • TDC: Tagless DRAM Cache.  
           S. R. Swamy Saranam , Madhu Mutyam
          Appeared in 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp.88-93, Jul 2018
  • TTLG - An Efficient Tensor Transposition Library for GPUs.  
           Venkata Naga Jyothi V , Arjun Suresh , Aravind Sukumaran-Rajam , Jinsung Kim , Changwan Hong , Ajay Panyala , Sriram Krishnamoorthy , V. Krishna Nandivada , Rohit Kumar Srivastava , P. Sadayappan
          Appeared in 2018 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2018, Vancouver, BC, Canada, May 21-25, 2018, pp.578-588, May 2018

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